State Machine Modeling For HDLs

For efficient code generation from State Machine models into Hardware Description Languages (HDL) such as VHDL, Verilog and SystemC, apply the design practices outlined in this topic.

In an HDL State Machine model, the following are expected:

Designate Driving Triggers
Establish Port-Trigger Mapping
Active State Logic

How to

Topic

Detail

See also

Designate Driving Triggers

A 'change' trigger is deemed as an asynchronous trigger if the following two conditions are satisfied:
1.There is a transition from the actual submachine state (which encapsulates the actual logic) triggered by it
2.The target state of that transition has a self transition triggered by the same trigger
Asynchronous triggers should be modeled according to the following pattern:
1.The trigger should be of type Change (specification: true / false)
2.The active state (Submachine State) should have a transition trigger by it.
3.The target state of the triggered transition should have a self transition with the same trigger
A trigger of type time, which triggers the transitions to the active state (Submachine State) is deemed as the Clock; the specification of this trigger should be specific to the target language:

Trigger Type

Language

Specification

Positive Edge Triggered

Negative Edge Triggered

 

Time

VHDL

rising_edge

falling_edge

Verilog

posedge

negedge

SystemC

positive

negative

 

State Machine Diagrams

Trigger

Establish Port-Trigger Mapping

After successfully modeling the different operating modes of the component, and the triggers associated with them, you must associate the triggers with the component's ports

A Dependency relationship from the Port to the associated trigger is used to signify their association

Class_HDL

 

 

Active State Logic

The first two aspects, above, put in place the preliminaries required for efficient interpretation of the hardware components.

The actual State Machine logic is now modeled within the Active (Submachine) state.

 

 

Notes

To be able to generate code from behavioral models, all behavioral constructs should be contained within a Class
The current code generation engine supports only one clock trigger for a component

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