VHDL Conventions

Enterprise Architect supports round-trip engineering of VHDL, where the following conventions are used.

Reference

Stereotypes

Stereotype

Applies To

Corresponds To

architecture

Class

An architecture.

asynchronous

Method

An asynchronous process.

configuration

Method

A configuration.

enumeration

Inner Class

An enum type.

entity

Interface

An entity.

part

Attribute

A component instantiation.

port

Attribute

A port.

signal

Attribute

A signal declaration.

struct

Inner Class

A record definition.

synchronous

Method

A synchronous process.

typedef

Inner Class

A type or subtype definition.

 
Tagged Values

Tag

Applies To

Corresponds To

isGeneric

Attribute (port)

The port declaration in a generic interface.

isSubType

Inner Class (typedef)

A subtype definition.

kind

Attribute (signal)

The signal kind (such as register, bus).

mode

Attribute (port)

The port mode (in, out, inout, buffer, linkage).

portmap

Attribute (part)

The generic / port map of the component instantiated.

sensitivity

Method (synchronous)

The sensitivity list of a synchronous process.

type

Inner Class (typedef)

The type indication of a type declaration.

typeNameSpace

Attribute (part)

The type namespace of the instantiated component.

VHDL Toolbox Pages:

To access the VHDL pages of the Toolbox, select the More tools | HDL | VHDL Constructs menu option. Drag these icons onto a diagram to model a VHDL design.

Reference

Page

Item

Action

VHDL

Architecture

Define an architecture to be associated with a VHDL entity.

An architecture-stereotyped Class element.

 

Entity

Define a VHDL entity to contain the Port definitions.

An entity-stereotyped interface element.

 

Enumeration

Define an Enumerated Type.

An Enumeration element.

 

Struct

Define a VHDL record.

A struct-stereotyped Class element.

 

Typedef

Define a VHDL type or subtype.

A typedef-stereotyped Class element.

VHDL Features

Port

Define a VHDL Port.

A port-stereotyped attribute.

 

Part

Define a VHDL component instantiation.

A part-stereotyped attribute.

 

Signal

Define a VHDL signal.

A signal-stereotyped attribute.

 

Procedure

Concurrent
Sequential
Configuration.

Define a VHDL process:

An asynchronous-stereotyped method
A synchronous-stereotyped method
A configuration-stereotyped method

 

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