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VHDL Conventions

Enterprise Architect supports round-trip engineering of VHDL, where these conventions are used.

Stereotypes

Stereotype

Applies To

See also

architecture

Class

Corresponds To: An architecture.

asynchronous

Method

Corresponds To: An asynchronous process.

configuration

Method

Corresponds To: A configuration.

enumeration

Inner Class

Corresponds To: An enumerated type.

entity

Interface

Corresponds To: An entity.

part

Attribute

Corresponds To: A component instantiation.

port

Attribute

Corresponds To: A port.

signal

Attribute

Corresponds To: A signal declaration.

struct

Inner Class

Corresponds To: A record definition.

synchronous

Method

Corresponds To: A synchronous process.

typedef

Inner Class

Corresponds To: A type or subtype definition.

Tagged Values

Tag

Applies To

See also

isGeneric

Attribute (port)

Corresponds To: The 'port' declaration in a generic interface.

isSubType

Inner Class (typedef)

Corresponds To: A subtype definition.

kind

Attribute (signal)

Corresponds To: The signal kind (such as 'register', 'bus').

mode

Attribute (port)

Corresponds To: The port mode ('in', 'out', 'inout', 'buffer', 'linkage').

portmap

Attribute (part)

Corresponds To: The generic / port map of the component instantiated.

sensitivity

Method (synchronous)

Corresponds To: The 'sensitivity' list of a synchronous process.

type

Inner Class (typedef)

Corresponds To: The 'type' indication of a 'type' declaration.

typeNameSpace

Attribute (part)

Corresponds To: The 'type' namespace of the instantiated component.

VHDL Toolbox Pages

Access

To model a VHDL design, drag icons from the VHDL toolbox pages and drop them on your diagram.

Ribbon

Design > Diagram > Toolbox : More tools | HDL | VHDL Constructs

Keyboard Shortcuts

Alt+5 : More tools | HDL | VHDL Constructs

Other

You can display or hide the Diagram Toolbox by clicking on the or icons at the left-hand end of the Caption Bar at the top of the Diagram View.

VHDL Toolbox Page

Item

Action

Architecture

Defines an architecture to be associated with a VHDL entity.

An architecture-stereotyped Class element.

Entity

Defines a VHDL entity to contain the Port definitions.

An entity-stereotyped interface element.

Enumeration

Defines an Enumerated Type.

An Enumeration element.

Struct

Defines a VHDL record.

A struct-stereotyped Class element.

Typedef

Defines a VHDL type or subtype.

A typedef-stereotyped Class element.

VHDL Features Toolbox Page

Item

Action

Part

Defines a VHDL component instantiation.

A part-stereotyped attribute.

Port

Defines a VHDL Port.

A port-stereotyped attribute.

Signal

Defines a VHDL signal.

A signal-stereotyped attribute.

Procedure

Defines a VHDL process:

  • Concurrent - An asynchronous-stereotyped method
  • Sequential - A synchronous-stereotyped method
  • Configuration - An configuration-stereotyped method

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