Verilog Conventions

Enterprise Architect supports round-trip engineering of Verilog, where the following conventions are used.

Stereotypes

Reference:

Stereotype

Applies To

Corresponds To

asynchronous

Method

A concurrent process.

enumeration

Inner Class

An enum type.

initializer

Method

An initializer process.

module

Class

A module.

part

Attribute

A component instantiation.

port

Attribute

A port.

synchronous

Method

A sequential process.

Tagged Values

Reference:

Tag

Applies To

Corresponds To

kind

Attribute (signal)

The signal kind (such as register, bus).

mode

Attribute (port)

The port mode (in, out, inout).

Portmap

Attribute (part)

The generic / port map of the component instantiated.

sensitivity

Method

The sensitivity list of a sequential process.

type

Attribute

The range or type value of an attribute.

Verilog Toolbox Pages

To access the Verilog pages of the Toolbox, select the More tools | HDL | Verilog Constructs menu option. Drag these icons onto a diagram to model a Verilog design.

Reference:

Page

Item

Action

Verilog

Module

Define a Verilog Module.

A module-stereotyped Class element.

 

Enumeration

Define an Enumerated Type.

An enumeration-stereotyped Class element.

Verilog Features

Port

Define a Verilog Port.

A port-stereotyped attribute.

 

Part

Define a Verilog component instantiation

A part-stereotyped attribute.

 

Attribute

Define an attribute.

 

Procedure

  • Concurrent
  • Sequential
  • Initializer.

Define a Verilog process:

  • An asynchronous-stereotyped method
  • A synchronous-stereotyped method
  • An initializer-stereotyped method

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