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StateMachine Modeling For HDLs
For efficient code generation from StateMachine models into Hardware Description Languages (HDL) such as VHDL, Verilog and SystemC, apply these design practices.
In an HDL StateMachine model, you might expect to:
- Designate Driving Triggers
- Establish Port–Trigger Mapping
- Add to Active State Logic
Aspect
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Designate Driving Triggers |
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State Machine Diagrams Trigger |
Establish Port-Trigger Mapping |
After successfully modeling the different operating modes of the component, and the Triggers associated with them, you must associate the Triggers with the component's Ports. A Dependency relationship from the Port to the associated Trigger is used to signify their association |
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Active State Logic |
The first two aspects put in place the preliminaries required for efficient interpretation of the hardware components. The actual StateMachine logic is now modeled within the Active (Submachine) state. |
Notes
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