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StateMachine Modeling For HDLs

For efficient code generation from StateMachine models into Hardware Description Languages (HDL) such as VHDL, Verilog and SystemC, apply these design practices.

In an HDL StateMachine model, you might expect to:

  • Designate Driving Triggers
  • Establish Port–Trigger Mapping
  • Add to Active State Logic




See also

Designate Driving Triggers

  • A 'change' trigger is deemed to be an asynchronous trigger if these two conditions are satisfied:
         -  There is a transition from the actual submachine state (which encapsulates the actual logic) triggered by it
         -  The target state of that transition has a self transition triggered by the same trigger
  • Asynchronous triggers should be modeled according to this pattern:
         -  The trigger should be of type Change (specification: True / False)
         -  The active state (Submachine State) should have a transition trigger by it
         -  The target state of the triggered transition should have a self transition with the same trigger
  • A trigger of type 'time', which triggers the transitions to the active state (Submachine State) is deemed as the Clock; the specification of this trigger should be specific to the target language:
         -  VHDL - rising_edge - falling_edge
         -  Verilog - posedge - negedge
         -  SystemC - positive - negative

State Machine Diagrams Trigger

Establish Port-Trigger Mapping

After successfully modeling the different operating modes of the component, and the Triggers associated with them, you must associate the Triggers with the component's Ports.

A Dependency relationship from the Port to the associated Trigger is used to signify their association

Active State Logic

The first two aspects put in place the preliminaries required for efficient interpretation of the hardware components.

The actual StateMachine logic is now modeled within the Active (Submachine) state.


  • To be able to generate code from behavioral models, all behavioral constructs should be contained within a Class
  • The current code generation engine supports only one clock trigger for a component

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