Please note : This help page is not for the latest version of Enterprise Architect. The latest help can be found here.

Prev Next

Digital Electronics Simulation Example

For this example, we walk through the creation of a SysPhS model for a simple digital electronic circuit, and then use a simulation to predict and chart the behavior of that circuit.

This example works with components that are not included with the SysPhS common components, so it runs through the process for creating Blocks to match the external components from scratch. For a webinar demonstrating this, see the link in Learn More at the end of the topic.


Running this simulation requires either:

  • OpenModelica or
  • MATLAB's Simulink

Circuit Diagram - a Digital Frequency Divider

The digital electronic circuit we are going to model is shown in this figure, which uses standard electronic circuit notation.

The circuit in this example includes a pulsed digital signal source, four Flip-Flops and a logical Boolean true state to form a simple frequency divider circuit.

Create SysML Model

This table shows how we can build a complete SysML model to represent the circuit, starting at the lowest level types and building up the model one step at a time.




In SysML, using SysPhS, the circuit and each of the component-types can be represented using a Block. 

Firstly create a Block Definition diagram (BDD) under a Package called 'Digital Model'.

In the BDD, you will create a set of components for the circuit, as SysML Blocks. The circuit contains representations of four Part-types - a pulsed digital signal source, a Flip-Flop, a boolean Port and a logical boolean true state. These Parts are of different types, with different behaviors.

Create a SysPhS Block for each of the Part types. The Parts for the circuit Internal Block Definition (IBD), will be connected through Ports, which represent electrical pins. These must be defined in the BDD.

This figure shows the BDD, with Blocks defining the types of component used.

Note that these Blocks are created from the SysPhS Toolbox using either Modelica Blocks or Simulink Blocks. You can type these Blocks to both tools.

For more information see the Setting Blocks as Both Modelica and Simulink Help topic.

Setting Modelica and Simulink Path

In order to define a Block specific to Modelica or Simulink you need to access the Component's Path in the respective application, then set this in the Block's Properties.

For example we can find the Flip-Flop component in Modelica.

We then copy that to the Block's properties.

For more details see the Creating Modelica Specific Blocks and Creating Simulink Specific Blocks Help topics.

PhS Ports

For setting Ports on the Blocks (in this case the Flip-Flop Clock Port) you drag either a Modelica or a Simulink PhS Port onto the Block. This Port must then be typed as a BooleanInSignal.


  • For Simulink the ordering on creating the Ports is critical - see Simulink Port Ordering in the Creating Simulink and Simscape Specific Blocks Help topic
  • These Ports can be set to both Modelica and Simulink by adding the stereotype for the other Port-type

Common Types

As a starter for all SysPhS models you must ensure that the SysPhS common types are loaded in the repository and referenced in the new model, using the Package Import connector. For more information see the Referencing the SysPhS Simulation Libraries Help Topic.

The Value Types used for the Ports are pre-defined in the SysPhS Simulation Libraries. The two key types used are the BooleanInSignal and the BooleanOutSignal ValueTypes.

This figure shows the Flip-Flop Block in the Block Definition diagram, with the Clock Port set to the BooleanInSignal ValueType and this being referenced in the Browser window.

Phs Constants

The Clock and Boolean-true Blocks both have properties defined in their respective components in MATLAB and Modelica.

Let's use the Clock as an example. For this component-type, in both Simulink and Modelica, we need to set a value for the period of each pulse and the width of each pulse. These Properties must be set and typed. The value of the Properties will be set in the IBD, the Parametric diagram or possibly in the simulation Datasets.

To set the property defining the period:

  • Drag a PhsConstant from the SysPhS toolbox onto the Clock
  • Delete the element from the diagram to show this in its compartment
  • In the Properties window, Properties tab, select the 'Type' field
  • Click on [...] and select 'Time' as the type

For setting the values in the individual component (Part), see the Initial Values row in this table.

Internal Structure - the Circuit

For the internal structure we create a Block with a child IBD diagram.

  • Create a Block for a Flip-Flop circuit
  • Under this Block create an Internal Block Definition (IBD) diagram using the context menu option
    Create New Child Diagram | Internal Block Definition diagram
  • Double-click to open the IBD
  • Set the diagram to only show the Port's name, using:
         -  F5 | Element | Element Appearance
  • Then unset these two options:
         -  Show Stereotypes
         -  Show Property Type
    This will then show only the Port and Type

On the IBD you create Parts and connect them:

  • From the Browser window, drag the Blocks onto the IBD as Parts (Properties)
  • To view these Parts in compartments, delete them from the diagram
    Note: Set the Paste option for 'Structural Elements' to 'ALL'
  • Add a Clock, four Flip-Flops and a table
  • Add four digital Ports to the boundary of the Counter IBD


To model the wiring up of these components:

  • Create connections between the Ports with connectors of type 'Connector'

Notice that this follows the same structure as the original circuit diagram, but the symbols for each component have been replaced with properties typed by the Blocks we have defined.

Initial Values

The digital pulse source is a DigitalClock component in Modelica and Simulink. This requires two parameters - 'Period' and 'Width', as shown in the Modelica editor.

The values of these parameters must be set in the IBD Part 'Clk', in the Properties window 'Property' tab, 'Initial' field

The J & K Ports require a fixed logical 'True' state. This is defined using a Table set to 'true' using an initial value, as shown here for Modelica.

On returning to the BDD you should now have the Counter Block shown as:

Configure Simulation Behavior

This table shows the detailed steps of the configuration of SysMLSim.



Create a SysMLSimConfiguration Artifact

  • Open the Block Definition diagram
  • Click on the open space in the diagram
  • Press the Spacebar
  • From the 'Artifacts' sub-menu, select 'SysMLSim Configuration'
    This creates a new SysMLSim Configuration Artifact

Set the Package

  • Double-click on the SysMLSim Configuration Artifact
    This opens the Configure SysML Configuration window
  • In the 'Package' field, click on the [...] button and select the Package containing the SysML diagram

Set Modelica or Simulink

In the top drop-down select which simulation tool to use:

  • Modelica
  • Simulink

For more details on these settings, see the Configure SysML Simulation Help topic.

Set the Block to Simulate

  • In the left-hand list, under 'Block', find 'InvertOpAmp'
  • In the 'Value' column, click on the drop-down and select 'SysMLSimModel'

Select Properties to Plot

You can now select the Properties to be plotted:

  • In the right-hand pane, select the Ports to plot

Run Simulation

On the 'Simulation' page, click on the Solve button. This shows an example of the plot generated in:



In the legend you can see Port 2 is selected, whereas the other Ports have been de-selected to show a simple Plot.

View the Model in Modelica or Simulink

To view the generated model in the external applications, Modelica or Simulink, see the Viewing the Generated Model Help topic. Also see the tips for debugging any issues in the generated code, in the SysPhS Debugging Tips Help topic.

Learn More